@=========================== RCC ===========================@
.equ RCC_BASE, 0x40021000 @ (Reset and clock control) 
    .equ RCC_CR, RCC_BASE + 0x0 @ (Clock control register) 
        .equ RCC_PLLRDY_Shift, 25   @ bitWidth 1 (PLL clock ready flag)  
        .equ RCC_PLLON_Shift, 24   @ bitWidth 1 (PLL enable bit)  
        .equ RCC_RTCPRE_Shift, 20   @ bitWidth 2 (TC/LCD prescaler)  
        .equ RCC_CSSLSEON_Shift, 19   @ bitWidth 1 (Clock security system on HSE enable  bit)  
        .equ RCC_HSEBYP_Shift, 18   @ bitWidth 1 (HSE clock bypass bit)  
        .equ RCC_HSERDY_Shift, 17   @ bitWidth 1 (HSE clock ready flag)  
        .equ RCC_HSEON_Shift, 16   @ bitWidth 1 (HSE clock enable bit)  
        .equ RCC_MSIRDY_Shift, 9   @ bitWidth 1 (MSI clock ready flag)  
        .equ RCC_MSION_Shift, 8   @ bitWidth 1 (MSI clock enable bit)  
        .equ RCC_HSI16DIVF_Shift, 4   @ bitWidth 1 (HSI16DIVF)  
        .equ RCC_HSI16DIVEN_Shift, 3   @ bitWidth 1 (HSI16DIVEN)  
        .equ RCC_HSI16RDYF_Shift, 2   @ bitWidth 1 (Internal high-speed clock ready  flag)  
        .equ RCC_HSI16KERON_Shift, 1   @ bitWidth 1 (High-speed internal clock enable bit for  some IP kernels)  
        .equ RCC_HSI16ON_Shift, 0   @ bitWidth 1 (16 MHz high-speed internal clock  enable)  
 
    .equ RCC_ICSCR, RCC_BASE + 0x4 @ (Internal clock sources calibration  register) 
        .equ RCC_MSITRIM_Shift, 24   @ bitWidth 8 (MSI clock trimming)  
        .equ RCC_MSICAL_Shift, 16   @ bitWidth 8 (MSI clock calibration)  
        .equ RCC_MSIRANGE_Shift, 13   @ bitWidth 3 (MSI clock ranges)  
        .equ RCC_HSI16TRIM_Shift, 8   @ bitWidth 5 (High speed internal clock  trimming)  
        .equ RCC_HSI16CAL_Shift, 0   @ bitWidth 8 (nternal high speed clock  calibration)  
 
    .equ RCC_CRRCR, RCC_BASE + 0x8 @ (Clock recovery RC register) 
        .equ RCC_HSI48CAL_Shift, 8   @ bitWidth 8 (48 MHz HSI clock  calibration)  
        .equ RCC_HSI48RDY_Shift, 1   @ bitWidth 1 (48MHz HSI clock ready flag)  
        .equ RCC_HSI48ON_Shift, 0   @ bitWidth 1 (48MHz HSI clock enable bit)  
 
    .equ RCC_CFGR, RCC_BASE + 0xC @ (Clock configuration register) 
        .equ RCC_MCOPRE_Shift, 28   @ bitWidth 3 (Microcontroller clock output  prescaler)  
        .equ RCC_MCOSEL_Shift, 24   @ bitWidth 3 (Microcontroller clock output  selection)  
        .equ RCC_PLLDIV_Shift, 22   @ bitWidth 2 (PLL output division)  
        .equ RCC_PLLMUL_Shift, 18   @ bitWidth 4 (PLL multiplication factor)  
        .equ RCC_PLLSRC_Shift, 16   @ bitWidth 1 (PLL entry clock source)  
        .equ RCC_STOPWUCK_Shift, 15   @ bitWidth 1 (Wake-up from stop clock  selection)  
        .equ RCC_PPRE2_Shift, 11   @ bitWidth 3 (APB high-speed prescaler  APB2)  
        .equ RCC_PPRE1_Shift, 8   @ bitWidth 3 (APB low-speed prescaler  APB1)  
        .equ RCC_HPRE_Shift, 4   @ bitWidth 4 (AHB prescaler)  
        .equ RCC_SWS_Shift, 2   @ bitWidth 2 (System clock switch status)  
        .equ RCC_SW_Shift, 0   @ bitWidth 2 (System clock switch)  
 
    .equ RCC_CIER, RCC_BASE + 0x10 @ (Clock interrupt enable  register) 
        .equ RCC_CSSLSE_Shift, 7   @ bitWidth 1 (LSE CSS interrupt flag)  
        .equ RCC_HSI48RDYIE_Shift, 6   @ bitWidth 1 (HSI48 ready interrupt flag)  
        .equ RCC_MSIRDYIE_Shift, 5   @ bitWidth 1 (MSI ready interrupt flag)  
        .equ RCC_PLLRDYIE_Shift, 4   @ bitWidth 1 (PLL ready interrupt flag)  
        .equ RCC_HSERDYIE_Shift, 3   @ bitWidth 1 (HSE ready interrupt flag)  
        .equ RCC_HSI16RDYIE_Shift, 2   @ bitWidth 1 (HSI16 ready interrupt flag)  
        .equ RCC_LSERDYIE_Shift, 1   @ bitWidth 1 (LSE ready interrupt flag)  
        .equ RCC_LSIRDYIE_Shift, 0   @ bitWidth 1 (LSI ready interrupt flag)  
 
    .equ RCC_CIFR, RCC_BASE + 0x14 @ (Clock interrupt flag register) 
        .equ RCC_CSSHSEF_Shift, 8   @ bitWidth 1 (Clock Security System Interrupt  flag)  
        .equ RCC_CSSLSEF_Shift, 7   @ bitWidth 1 (LSE Clock Security System Interrupt  flag)  
        .equ RCC_HSI48RDYF_Shift, 6   @ bitWidth 1 (HSI48 ready interrupt flag)  
        .equ RCC_MSIRDYF_Shift, 5   @ bitWidth 1 (MSI ready interrupt flag)  
        .equ RCC_PLLRDYF_Shift, 4   @ bitWidth 1 (PLL ready interrupt flag)  
        .equ RCC_HSERDYF_Shift, 3   @ bitWidth 1 (HSE ready interrupt flag)  
        .equ RCC_HSI16RDYF_Shift, 2   @ bitWidth 1 (HSI16 ready interrupt flag)  
        .equ RCC_LSERDYF_Shift, 1   @ bitWidth 1 (LSE ready interrupt flag)  
        .equ RCC_LSIRDYF_Shift, 0   @ bitWidth 1 (LSI ready interrupt flag)  
 
    .equ RCC_CICR, RCC_BASE + 0x18 @ (Clock interrupt clear register) 
        .equ RCC_CSSHSEC_Shift, 8   @ bitWidth 1 (Clock Security System Interrupt  clear)  
        .equ RCC_CSSLSEC_Shift, 7   @ bitWidth 1 (LSE Clock Security System Interrupt  clear)  
        .equ RCC_HSI48RDYC_Shift, 6   @ bitWidth 1 (HSI48 ready Interrupt  clear)  
        .equ RCC_MSIRDYC_Shift, 5   @ bitWidth 1 (MSI ready Interrupt clear)  
        .equ RCC_PLLRDYC_Shift, 4   @ bitWidth 1 (PLL ready Interrupt clear)  
        .equ RCC_HSERDYC_Shift, 3   @ bitWidth 1 (HSE ready Interrupt clear)  
        .equ RCC_HSI16RDYC_Shift, 2   @ bitWidth 1 (HSI16 ready Interrupt  clear)  
        .equ RCC_LSERDYC_Shift, 1   @ bitWidth 1 (LSE ready Interrupt clear)  
        .equ RCC_LSIRDYC_Shift, 0   @ bitWidth 1 (LSI ready Interrupt clear)  
 
    .equ RCC_IOPRSTR, RCC_BASE + 0x1C @ (GPIO reset register) 
        .equ RCC_IOPHRST_Shift, 7   @ bitWidth 1 (I/O port H reset)  
        .equ RCC_IOPDRST_Shift, 3   @ bitWidth 1 (I/O port D reset)  
        .equ RCC_IOPCRST_Shift, 2   @ bitWidth 1 (I/O port A reset)  
        .equ RCC_IOPBRST_Shift, 1   @ bitWidth 1 (I/O port B reset)  
        .equ RCC_IOPARST_Shift, 0   @ bitWidth 1 (I/O port A reset)  
 
    .equ RCC_AHBRSTR, RCC_BASE + 0x20 @ (AHB peripheral reset register) 
        .equ RCC_CRYPRST_Shift, 24   @ bitWidth 1 (Crypto module reset)  
        .equ RCC_RNGRST_Shift, 20   @ bitWidth 1 (Random Number Generator module  reset)  
        .equ RCC_TOUCHRST_Shift, 16   @ bitWidth 1 (Touch Sensing reset)  
        .equ RCC_CRCRST_Shift, 12   @ bitWidth 1 (Test integration module  reset)  
        .equ RCC_MIFRST_Shift, 8   @ bitWidth 1 (Memory interface reset)  
        .equ RCC_DMARST_Shift, 0   @ bitWidth 1 (DMA reset)  
 
    .equ RCC_APB2RSTR, RCC_BASE + 0x24 @ (APB2 peripheral reset register) 
        .equ RCC_DBGRST_Shift, 22   @ bitWidth 1 (DBG reset)  
        .equ RCC_USART1RST_Shift, 14   @ bitWidth 1 (USART1 reset)  
        .equ RCC_SPI1RST_Shift, 12   @ bitWidth 1 (SPI 1 reset)  
        .equ RCC_ADCRST_Shift, 9   @ bitWidth 1 (ADC interface reset)  
        .equ RCC_TM12RST_Shift, 5   @ bitWidth 1 (TIM22 timer reset)  
        .equ RCC_TIM21RST_Shift, 2   @ bitWidth 1 (TIM21 timer reset)  
        .equ RCC_SYSCFGRST_Shift, 0   @ bitWidth 1 (System configuration controller  reset)  
 
    .equ RCC_APB1RSTR, RCC_BASE + 0x28 @ (APB1 peripheral reset register) 
        .equ RCC_LPTIM1RST_Shift, 31   @ bitWidth 1 (Low power timer reset)  
        .equ RCC_DACRST_Shift, 29   @ bitWidth 1 (DAC interface reset)  
        .equ RCC_PWRRST_Shift, 28   @ bitWidth 1 (Power interface reset)  
        .equ RCC_CRSRST_Shift, 27   @ bitWidth 1 (Clock recovery system  reset)  
        .equ RCC_USBRST_Shift, 23   @ bitWidth 1 (USB reset)  
        .equ RCC_I2C2RST_Shift, 22   @ bitWidth 1 (I2C2 reset)  
        .equ RCC_I2C1RST_Shift, 21   @ bitWidth 1 (I2C1 reset)  
        .equ RCC_LPUART1RST_Shift, 18   @ bitWidth 1 (LPUART1 reset)  
        .equ RCC_LPUART12RST_Shift, 17   @ bitWidth 1 (UART2 reset)  
        .equ RCC_SPI2RST_Shift, 14   @ bitWidth 1 (SPI2 reset)  
        .equ RCC_WWDRST_Shift, 11   @ bitWidth 1 (Window watchdog reset)  
        .equ RCC_LCDRST_Shift, 9   @ bitWidth 1 (LCD reset)  
        .equ RCC_TIM6RST_Shift, 4   @ bitWidth 1 (Timer 6 reset)  
        .equ RCC_TIM2RST_Shift, 0   @ bitWidth 1 (Timer2 reset)  
 
    .equ RCC_IOPENR, RCC_BASE + 0x2C @ (GPIO clock enable register) 
        .equ RCC_IOPHEN_Shift, 7   @ bitWidth 1 (I/O port H clock enable  bit)  
        .equ RCC_IOPDEN_Shift, 3   @ bitWidth 1 (I/O port D clock enable  bit)  
        .equ RCC_IOPCEN_Shift, 2   @ bitWidth 1 (IO port A clock enable bit)  
        .equ RCC_IOPBEN_Shift, 1   @ bitWidth 1 (IO port B clock enable bit)  
        .equ RCC_IOPAEN_Shift, 0   @ bitWidth 1 (IO port A clock enable bit)  
 
    .equ RCC_AHBENR, RCC_BASE + 0x30 @ (AHB peripheral clock enable  register) 
        .equ RCC_CRYPEN_Shift, 24   @ bitWidth 1 (Crypto clock enable bit)  
        .equ RCC_RNGEN_Shift, 20   @ bitWidth 1 (Random Number Generator clock enable  bit)  
        .equ RCC_TOUCHEN_Shift, 16   @ bitWidth 1 (Touch Sensing clock enable  bit)  
        .equ RCC_CRCEN_Shift, 12   @ bitWidth 1 (CRC clock enable bit)  
        .equ RCC_MIFEN_Shift, 8   @ bitWidth 1 (NVM interface clock enable  bit)  
        .equ RCC_DMAEN_Shift, 0   @ bitWidth 1 (DMA clock enable bit)  
 
    .equ RCC_APB2ENR, RCC_BASE + 0x34 @ (APB2 peripheral clock enable  register) 
        .equ RCC_DBGEN_Shift, 22   @ bitWidth 1 (DBG clock enable bit)  
        .equ RCC_USART1EN_Shift, 14   @ bitWidth 1 (USART1 clock enable bit)  
        .equ RCC_SPI1EN_Shift, 12   @ bitWidth 1 (SPI1 clock enable bit)  
        .equ RCC_ADCEN_Shift, 9   @ bitWidth 1 (ADC clock enable bit)  
        .equ RCC_MIFIEN_Shift, 7   @ bitWidth 1 (MiFaRe Firewall clock enable  bit)  
        .equ RCC_TIM22EN_Shift, 5   @ bitWidth 1 (TIM22 timer clock enable  bit)  
        .equ RCC_TIM21EN_Shift, 2   @ bitWidth 1 (TIM21 timer clock enable  bit)  
        .equ RCC_SYSCFGEN_Shift, 0   @ bitWidth 1 (System configuration controller clock  enable bit)  
 
    .equ RCC_APB1ENR, RCC_BASE + 0x38 @ (APB1 peripheral clock enable  register) 
        .equ RCC_LPTIM1EN_Shift, 31   @ bitWidth 1 (Low power timer clock enable  bit)  
        .equ RCC_DACEN_Shift, 29   @ bitWidth 1 (DAC interface clock enable  bit)  
        .equ RCC_PWREN_Shift, 28   @ bitWidth 1 (Power interface clock enable  bit)  
        .equ RCC_CRSEN_Shift, 27   @ bitWidth 1 (Clock recovery system clock enable  bit)  
        .equ RCC_USBEN_Shift, 23   @ bitWidth 1 (USB clock enable bit)  
        .equ RCC_I2C2EN_Shift, 22   @ bitWidth 1 (I2C2 clock enable bit)  
        .equ RCC_I2C1EN_Shift, 21   @ bitWidth 1 (I2C1 clock enable bit)  
        .equ RCC_LPUART1EN_Shift, 18   @ bitWidth 1 (LPUART1 clock enable bit)  
        .equ RCC_USART2EN_Shift, 17   @ bitWidth 1 (UART2 clock enable bit)  
        .equ RCC_SPI2EN_Shift, 14   @ bitWidth 1 (SPI2 clock enable bit)  
        .equ RCC_WWDGEN_Shift, 11   @ bitWidth 1 (Window watchdog clock enable  bit)  
        .equ RCC_LCDEN_Shift, 9   @ bitWidth 1 (LCD clock enable bit)  
        .equ RCC_TIM6EN_Shift, 4   @ bitWidth 1 (Timer 6 clock enable bit)  
        .equ RCC_TIM2EN_Shift, 0   @ bitWidth 1 (Timer2 clock enable bit)  
 
    .equ RCC_IOPSMEN, RCC_BASE + 0x3C @ (GPIO clock enable in sleep mode  register) 
        .equ RCC_IOPHSMEN_Shift, 7   @ bitWidth 1 (IOPHSMEN)  
        .equ RCC_IOPDSMEN_Shift, 3   @ bitWidth 1 (IOPDSMEN)  
        .equ RCC_IOPCSMEN_Shift, 2   @ bitWidth 1 (IOPCSMEN)  
        .equ RCC_IOPBSMEN_Shift, 1   @ bitWidth 1 (IOPBSMEN)  
        .equ RCC_IOPASMEN_Shift, 0   @ bitWidth 1 (IOPASMEN)  
 
    .equ RCC_AHBSMENR, RCC_BASE + 0x40 @ (AHB peripheral clock enable in sleep mode  register) 
        .equ RCC_CRYPSMEN_Shift, 24   @ bitWidth 1 (Crypto clock enable during sleep mode  bit)  
        .equ RCC_RNGSMEN_Shift, 20   @ bitWidth 1 (Random Number Generator clock enable  during sleep mode bit)  
        .equ RCC_TOUCHSMEN_Shift, 16   @ bitWidth 1 (Touch Sensing clock enable during sleep  mode bit)  
        .equ RCC_CRCSMEN_Shift, 12   @ bitWidth 1 (CRC clock enable during sleep mode  bit)  
        .equ RCC_SRAMSMEN_Shift, 9   @ bitWidth 1 (SRAM interface clock enable during sleep  mode bit)  
        .equ RCC_MIFSMEN_Shift, 8   @ bitWidth 1 (NVM interface clock enable during sleep  mode bit)  
        .equ RCC_DMASMEN_Shift, 0   @ bitWidth 1 (DMA clock enable during sleep mode  bit)  
 
    .equ RCC_APB2SMENR, RCC_BASE + 0x44 @ (APB2 peripheral clock enable in sleep mode  register) 
        .equ RCC_DBGSMEN_Shift, 22   @ bitWidth 1 (DBG clock enable during sleep mode  bit)  
        .equ RCC_USART1SMEN_Shift, 14   @ bitWidth 1 (USART1 clock enable during sleep mode  bit)  
        .equ RCC_SPI1SMEN_Shift, 12   @ bitWidth 1 (SPI1 clock enable during sleep mode  bit)  
        .equ RCC_ADCSMEN_Shift, 9   @ bitWidth 1 (ADC clock enable during sleep mode  bit)  
        .equ RCC_TIM22SMEN_Shift, 5   @ bitWidth 1 (TIM22 timer clock enable during sleep  mode bit)  
        .equ RCC_TIM21SMEN_Shift, 2   @ bitWidth 1 (TIM21 timer clock enable during sleep  mode bit)  
        .equ RCC_SYSCFGSMEN_Shift, 0   @ bitWidth 1 (System configuration controller clock  enable during sleep mode bit)  
 
    .equ RCC_APB1SMENR, RCC_BASE + 0x48 @ (APB1 peripheral clock enable in sleep mode  register) 
        .equ RCC_LPTIM1SMEN_Shift, 31   @ bitWidth 1 (Low power timer clock enable during  sleep mode bit)  
        .equ RCC_DACSMEN_Shift, 29   @ bitWidth 1 (DAC interface clock enable during sleep  mode bit)  
        .equ RCC_PWRSMEN_Shift, 28   @ bitWidth 1 (Power interface clock enable during  sleep mode bit)  
        .equ RCC_CRSSMEN_Shift, 27   @ bitWidth 1 (Clock recovery system clock enable  during sleep mode bit)  
        .equ RCC_USBSMEN_Shift, 23   @ bitWidth 1 (USB clock enable during sleep mode  bit)  
        .equ RCC_I2C2SMEN_Shift, 22   @ bitWidth 1 (I2C2 clock enable during sleep mode  bit)  
        .equ RCC_I2C1SMEN_Shift, 21   @ bitWidth 1 (I2C1 clock enable during sleep mode  bit)  
        .equ RCC_LPUART1SMEN_Shift, 18   @ bitWidth 1 (LPUART1 clock enable during sleep mode  bit)  
        .equ RCC_USART2SMEN_Shift, 17   @ bitWidth 1 (UART2 clock enable during sleep mode  bit)  
        .equ RCC_SPI2SMEN_Shift, 14   @ bitWidth 1 (SPI2 clock enable during sleep mode  bit)  
        .equ RCC_WWDGSMEN_Shift, 11   @ bitWidth 1 (Window watchdog clock enable during  sleep mode bit)  
        .equ RCC_LCDSMEN_Shift, 9   @ bitWidth 1 (LCD clock enable during sleep mode  bit)  
        .equ RCC_TIM6SMEN_Shift, 4   @ bitWidth 1 (Timer 6 clock enable during sleep mode  bit)  
        .equ RCC_TIM2SMEN_Shift, 0   @ bitWidth 1 (Timer2 clock enable during sleep mode  bit)  
 
    .equ RCC_CCIPR, RCC_BASE + 0x4C @ (Clock configuration register) 
        .equ RCC_HSI48MSEL_Shift, 26   @ bitWidth 1 (48 MHz HSI48 clock source selection  bit)  
        .equ RCC_LPTIM1SEL1_Shift, 19   @ bitWidth 1 (Low Power Timer clock source selection  bits)  
        .equ RCC_LPTIM1SEL0_Shift, 18   @ bitWidth 1 (LPTIM1SEL0)  
        .equ RCC_I2C1SEL1_Shift, 13   @ bitWidth 1 (I2C1 clock source selection  bits)  
        .equ RCC_I2C1SEL0_Shift, 12   @ bitWidth 1 (I2C1SEL0)  
        .equ RCC_LPUART1SEL1_Shift, 11   @ bitWidth 1 (LPUART1 clock source selection  bits)  
        .equ RCC_LPUART1SEL0_Shift, 10   @ bitWidth 1 (LPUART1SEL0)  
        .equ RCC_USART2SEL1_Shift, 3   @ bitWidth 1 (USART2 clock source selection  bits)  
        .equ RCC_USART2SEL0_Shift, 2   @ bitWidth 1 (USART2SEL0)  
        .equ RCC_USART1SEL1_Shift, 1   @ bitWidth 1 (USART1 clock source selection  bits)  
        .equ RCC_USART1SEL0_Shift, 0   @ bitWidth 1 (USART1SEL0)  
 
    .equ RCC_CSR, RCC_BASE + 0x50 @ (Control and status register) 
        .equ RCC_LPWRSTF_Shift, 31   @ bitWidth 1 (Low-power reset flag)  
        .equ RCC_WWDGRSTF_Shift, 30   @ bitWidth 1 (Window watchdog reset flag)  
        .equ RCC_IWDGRSTF_Shift, 29   @ bitWidth 1 (Independent watchdog reset  flag)  
        .equ RCC_SFTRSTF_Shift, 28   @ bitWidth 1 (Software reset flag)  
        .equ RCC_PORRSTF_Shift, 27   @ bitWidth 1 (POR/PDR reset flag)  
        .equ RCC_PINRSTF_Shift, 26   @ bitWidth 1 (PIN reset flag)  
        .equ RCC_OBLRSTF_Shift, 25   @ bitWidth 1 (OBLRSTF)  
        .equ RCC_RMVF_Shift, 24   @ bitWidth 1 (Remove reset flag)  
        .equ RCC_RTCRST_Shift, 19   @ bitWidth 1 (RTC software reset bit)  
        .equ RCC_RTCEN_Shift, 18   @ bitWidth 1 (RTC clock enable bit)  
        .equ RCC_RTCSEL_Shift, 16   @ bitWidth 2 (RTC and LCD clock source selection  bits)  
        .equ RCC_CSSLSED_Shift, 14   @ bitWidth 1 (CSS on LSE failure detection  flag)  
        .equ RCC_CSSLSEON_Shift, 13   @ bitWidth 1 (CSSLSEON)  
        .equ RCC_LSEDRV_Shift, 11   @ bitWidth 2 (LSEDRV)  
        .equ RCC_LSEBYP_Shift, 10   @ bitWidth 1 (External low-speed oscillator bypass  bit)  
        .equ RCC_LSERDY_Shift, 9   @ bitWidth 1 (External low-speed oscillator ready  bit)  
        .equ RCC_LSEON_Shift, 8   @ bitWidth 1 (External low-speed oscillator enable  bit)  
        .equ RCC_LSIRDY_Shift, 1   @ bitWidth 1 (Internal low-speed oscillator ready  bit)  
        .equ RCC_LSION_Shift, 0   @ bitWidth 1 (Internal low-speed oscillator  enable)
